The present invention relates to a sense circuit which read signals from a semiconductor memory. More specifically, the invention relates to a high-speed and highly stable sense circuit which is adapted to DRAM (dynamic random access memory) and SRAM (static random access memory) that operable at high speeds and that are highly densely integrated.
The conventional sense circuit in a memory is generally constructed as shown in FIG. 1. An improved system thereof has also been discussed in IEEE, International Solid-State Circuits Conference, 1986, pp. 262-263.
The coventional sense circuit is constructed as shown in FIG. 1. Here, the description deals with the sense circuit in a dynamic memory. It should, however, be noted that the sense circuit is constituted in the same manner even in a static memory by substituting the memory cells of the static memory for the memory array and the sense amplifiers.
In FIG. 1, reference numeral 1 denotes a dynamic memory cell array, 2 denotes a CMOS sense amplifier, 3 denotes a column switch, 4 denotes output line having an address signal which turns the gate of the column switch 3 on and off, 5 denotes a decoder for selecting the address, reference numerals 6A and 6B denotes I/O lines (inputs/output lines, common lines) for transmitting the signals, 8 and 20 denote load elemnets that apply potentials to the I/O lines 6A and 6B, 9 and 10 denote load capacitances that are parasitic on the I/O lines 6A and 6B, and reference numeral 12 denotes a voltage amplifier which amplifiers a difference in the siganl votage between the I/O lines 6A and 6B.
In the conventional sense circuit, the loads 20 and 8 are driven by a sense amplifier that serves as a signal source, and a difference in the signal votage that appears across the I/O lines 6A and 6B is amplified by the voltage amplifier 12 into a large voltage difference; i.e., information read by a sense amplifier is amplified and is produced.